Description
Data Patterns
Data format: DNRZ, DRZ (50% duty cycle)
Memory depth: 16 Kb
Data sequence: Preamble data, cycle data, PRWS23 (random data based on PRBS sequence 2x10E23 -1)
PRBS Patterns
2x10E23 – 1 (CCITT 0.151)
2x10EN – where n = 7, 10, 11
Zero Substitution: Zeros can be subsituted for data to extend the longest run of zeros.
Variable Mark Density: The ratio of 1s to total bits can be set to 1/8, 1/4, 1/2, 3/4, & 7/8.
External Clock Input: The external clock input on the data module is used to generate asynchronous data streams with respect to the mainframe clock.
External Input (start, gate): The external input on the data module is used to start and gate the data stream.
