Keysight 1661A Logic Analyzer 102 CH 100 MHz State 500 MHz Timing

Description

State and timing channels: 102 Setup/hold time: 3.5/0ns to 0/3.5ns State/timing memory depth: 4k on all channels, 8k on half channels Timing analysis modes and speeds (conventional): 250MHz on all channels, 500MHz on half channels Timing analysis modes and speeds (transitional): 125MHz on all channels, 250MHz on half channels Timing analysis modes and speeds (glitch): 125MHz on half channels State analysis speed: 100MHz Minimum detectable glitch width: 3.5ns